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d88_emit.py appends the 21 Usetup*Z stage-setup files (object placement, AI scripts, pads/nav) to the same data/pccg-<region>/ sidecar d69 produces. Without it the port has no setup data for any level and segfaults on load before frame 1 (this was mis-filed as D185 'd69 regression' — it was a missing pipeline step). Vendor d88_emit.py + its one local import d88_propdefs.py; run d43 -> d69 -> d88 --regen. Verified: fresh d43+d69+d88 from an assembled bundle produces pccg.bin (3604378 B, 74 rows) and pcmodels.bin byte-identical to the known-good sidecars; -level_09 and -level_20 boot crash-free against them.