mirror of
https://github.com/jkdansereau/goldeneye-pc-port.git
synced 2026-10-23 15:52:42 +02:00
James Dansereau
52539d10de
- README, LICENSE (MIT for the port layer), NOTICE, CONTRIBUTING. - Restructure docs: internals.md, porting-notes.md, dev-process.md + dev/agentic-development.md (the research write-up), dev/ (raw record). - Replace decomp status-badge CI with a PC-port validate workflow. - Remove session/agent scaffolding and stale planning docs from the tree. - Add .gitattributes (normalize line endings to LF); add screenshots. The pre-2026-08 history is the GoldenEye 007 decompilation by Larry Ficken (KholdFuzion) and contributors, preserved unchanged. The PC-port work from 2026-08-17 on is mine.
57 lines
2.1 KiB
C
57 lines
2.1 KiB
C
#ifndef PORT_PCCG_H
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#define PORT_PCCG_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* D69 (docs/internals.md): PC-layout stage bg/*.seg + Tbg_*_stanZ
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* sidecars -- same Plan-B pattern as D50/pcmodels.c.
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*
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* N64 bg/*.seg and Tbg_*_stanZ files are big-endian images with internal
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* self-relative 0x0Fxxxxxx offsets that the PC build cannot read in place
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* (D78-D81). tools_pc/d69_emit.py converts all of them offline to PC-layout
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* sidecars:
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* data/pccg-<region>/pccg.bin single concatenated image
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* data/pccg-<region>/manifest.csv name,offset,size (decimal)
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*
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* romdataInit reserves romSize + pcmodelsReserveSize() + pccgReserveSize()
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* at CART_BASE and pccgLoadSidecars() copies the sidecar image to
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* [CART_BASE+romSize+pcmodelsTotalSize(), ...) (right after the pcmodels
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* extension). pccgPatchTable() -- called once from the same
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* load_object_fill_header hook as pcmodelsPatchTable(), after obInit() has
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* run -- redirects every bg/stan entry's hw_address into the extension
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* region and sets rom_size to the PC (possibly re-compressed) size, so the
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* existing obLoadBGFileBytesAtOffset/_fileNameLoadToBank/decompressdata load
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* paths serve PC bytes unmodified.
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*/
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/* Bytes to reserve immediately after the pcmodels extension (0 = no sidecar
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* image found; the game boots but stage loads will fault as before D69).
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* romImg is the validated ROM image; the country byte at +0x3E selects the
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* region directory. */
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uint32_t pccgReserveSize(const uint8_t *romImg);
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/* Copy the sidecar image to base+... and parse the manifest. `base` is the
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* cart address immediately after the pcmodels extension (i.e.
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* cartBase + romSize + pcmodelsTotalSize()). Returns 1 on success. */
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int pccgLoadSidecars(uintptr_t base);
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/* One-shot patch of file_resource_table + resource_lookup_data_array for
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* every manifest row. Must run after obInit(). No-op if the sidecar image
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* is absent. */
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void pccgPatchTable(void);
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uint32_t pccgTotalSize(void);
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/* Cart address where the sidecar image lives (0 if absent). */
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uintptr_t pccgSidecarBase(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* PORT_PCCG_H */
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