James Dansereau 73dfa8d81f D126: objective sub-record ->next pointer growth desyncs propdef walk ...

criteria_picture (30) / criteria_roomentered (32) / criteria_deposit (33)
/ setup_objective_text (35) each end in a T*next list pointer that the
setup walk writes unconditionally (set_parent_cur_obj_* /
setup_briefing_text_entry_parent). On x86-64 the pointer widens 4->8B and
8-aligns at offset 16, making the struct 24B/6w (N64 16/20). d88_propdefs.py
emitted N64 size -> the runtime 8-byte ->next store clobbered the next
propdef record's header -> walk desync -> command indices drifted ~100 ->
setupDoor linkedDoor resolution landed on the wrong record -> crash.

Fixes C3r (Bunker2 -level_27), C4 (Depot -level_30), C6 (Surface2 -level_43)
in one change. Sweep 13 -> 16/21. Bunker1/Silo/Aztec/Archives/Egypt/Train
unregressed; d125_check.py 21/21 MATCH.

- tools_pc/d88_propdefs.py: PROPDEF_PC_BYTES[30/32/33/35]=24 + typed handler
- src/game/loadobjectmodel.c: sizepropdef PORT returns 6 for those types

2026-08-29 19:35:19 -04:00

..

golden

tools_pc: D115 golden frame baseline for regression diffing (-level_09 BUNKER1)

2026-08-29 10:38:23 -04:00

d43_chainbound.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_convert.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_cover.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_decode.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_emit.py

D112: fix d43_emit put_f32 byte-swap off-by-one (skeletal models collapsed)

2026-08-29 09:21:12 -04:00

d43_fullwalk.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_gdldump.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_gdlhist.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_gdlorder.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_gdlseq.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_invariants.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_layout1.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_layout.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_layoutprobe.c

PC port: phase 2 — Plan B executed (D50): offline model sidecars + port plumbing; texCopyGdls w1 fix

2026-08-23 10:22:03 -04:00

d43_lutscan.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_pointusage.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_seg5.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_seg5ops.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_seg5vtx2.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_seg5vtx.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_sizes2.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_sizes.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_tree_dump.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_vtxfmt.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d43_walk.py

PC port: phase 2 — D48 review: re-plan D43 as offline pre-conversion (Plan B)

2026-08-22 18:43:04 -04:00

d51_gdb.py

PC port: phase 2 — D59-D68 milestone: full intro renders; blocker is D69 (BG-file BE headers)

2026-08-24 03:27:29 -04:00

d69_emit.py

D88.5: byte-swap the stan tile id-hi half in the converter

2026-08-28 09:58:14 -04:00

d88_emit.py

D125: fix d88_emit.py:374 8-byte slice / 4-byte literal (Aztec C3 crash)

2026-08-29 19:12:52 -04:00

d88_layoutprobe.c

D88.4: propDefs record format spec + N64->PC converter (d88_propdefs.py)

2026-08-28 09:16:05 -04:00

d88_propdef_scan.py

D88.4: add propDefs region scanner (analysis helper, WIP)

2026-08-28 08:33:31 -04:00

d88_propdefs.py

D126: objective sub-record ->next pointer growth desyncs propdef walk

2026-08-29 19:35:19 -04:00

d125_check.py

D125: fix d88_emit.py:374 8-byte slice / 4-byte literal (Aztec C3 crash)

2026-08-29 19:12:52 -04:00

disasm.py

PC port: Phase 1.5 — root-cause D32 Part B (D33): ROM big-endian

2026-08-21 20:18:38 -04:00

framediff.py

D117: framediff.py visual-regression tool; root-cause frame nondeterminism

2026-08-29 10:49:15 -04:00

level_sweep.sh

M-13: 21-level sweep matrix + D123 (C1 fix) + D124 (C2 Jungle fix)

2026-08-29 16:36:18 -04:00

mtxtest.c

Repo cleanup: reference footage to docs/reference/, ignore local artifacts

2026-08-27 19:27:05 -04:00

pixcount.py

PC port: phase 2 — D59-D68 milestone: full intro renders; blocker is D69 (BG-file BE headers)

2026-08-24 03:27:29 -04:00

ppm2bmp.py

PC port: phase 2 — D59-D68 milestone: full intro renders; blocker is D69 (BG-file BE headers)

2026-08-24 03:27:29 -04:00

romverify.c

PC port: phase 1.5 — ROM dump verification groundwork

2026-08-21 20:29:03 -04:00