forked from Ports/goldeneye-pc-port
James Dansereau
daa2522511
F10 pad slider persistence (D489), glass collision hull (D490), A/B input harnesses (1964 virtual pad, GE_INPUTSCRIPT, live one-pad launcher), adjacent global struct reads (D491), vibration percent, D441 complete pointer-width census with high-arena tier-1 build, fix batches 1-5 and an ABI warning ratchet, playtest verification of D493-D502. Refs: D489 D490 D491 D492-D502 D441
24 lines
1.1 KiB
C
24 lines
1.1 KiB
C
#ifndef PORT_PORTADDR_H
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#define PORT_PORTADDR_H
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/* Stage B step 1 (STAGEB-ABI-DESIGN, D441 follow-on): the ONE place that
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* names the N64-DRAM arena windows. port/src/dram.c maps an 8 MB backing
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* store at BOTH views; everything that converts or range-checks an arena
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* address uses these instead of a literal, so moving the arena later (the
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* high-arena test flavour, macOS/ARM port_addr) is a change in one header.
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* Compile-time constants: no codegen change from the old literals. */
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/* Each define is #ifndef-guarded so a -D on the command line can override it
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* (the D441 high-arena test flavour: GE_HIGHARENA_BASE=0x90000000 adds
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* -DPORT_DRAM_V1_BASE=0x90000000 for C, CXX and ASM). Values unchanged. */
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#ifndef PORT_DRAM_V1_BASE
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#define PORT_DRAM_V1_BASE 0x70000000UL /* s32-safe "virtual" view (game RAM symbols) */
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#endif
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#ifndef PORT_DRAM_K0_BASE
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#define PORT_DRAM_K0_BASE 0x80000000UL /* KSEG0 mirror of V1 (same pages) */
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#endif
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#ifndef PORT_DRAM_SIZE
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#define PORT_DRAM_SIZE 0x00800000UL /* 8 MB, like an 8-MB-RAM N64 */
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#endif
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#endif /* PORT_PORTADDR_H */
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